1. Field of the Invention
The present invention relates generally to techniques for designing semiconductor devices and, in particular, to techniques for reducing timing violations in a semiconductor design.
2. Description of the Related Art
Increasing an operating frequency of an integrated circuit generally includes reducing delays through critical timing paths (i.e., paths that determine an operating frequency of an integrated circuit, typically the longest paths in the circuit). However, integrated circuits may include a number of transistors and interconnections that makes it burdensome to perform timing enhancements of a large number of critical timing paths. Accordingly, there is a need for a technique that reduces the number of critical timing paths for analysis to improve circuit performance.